library verilog;
use verilog.vl_types.all;
entity precise_divider is
    generic(
        DEVIDE_CNT      : integer := 6597070
    );
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        divide_clk      : out    vl_logic;
        divide_clken    : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of DEVIDE_CNT : constant is 1;
end precise_divider;
